Zhaoming Ding was born in Chongqing, China, in 1989. He received his B.S. degree in Microelectronics from University of Electronic Science and Technology of China, Chengdu, China, in 2012. He received his Ph.D. degree in 2018.
His research interests include analog, mixed-signal circuits, analog-to-digital converters and phase-locked loops.
Publication
- Z. Ding, X. Zhou, Q. Li. A 0.5–1.1V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator[J]. IEEE J. Solid-State Circuits
- Z. Ding, X. Zhou, Q. Li. A 0.5-1.1V 10b adaptive bypassing SAR ADC utilizing oscillation cycle information of VCO-based comparator[C]. in Symp. VLSI Circuits, Hawaii, 2018, 1-2
- Z. Ding, X. Zhou, Q. Li. Delta-measurement low-power SAR ADC architecture with adaptive threshold-first switching[C]. in IEEE Int. Symp. Circuits and Systems (ISCAS), Florence, 2018, 1-4
- Z. Ding, H. Liu, Q. Li. Phase-error cancellation technique for fast-lock phase-locked loop[J]. IET Circuits, Devices & Systems, 2016, 10(5): 417-422
- Z. Ding, H. Liu, Q. Li. A phase error cancellation technique for fast-lock PLL[C]. in IEEE ICSICT, Guilin, 2014, 1-3