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Lishan Lv (S’14) was born in Sichuan province of China, in 1990. He received the B.S. degree from School of Microelectronics and Solid-State Electronic, University of Electronic Science and Technology of China, Chengdu, China in 2012.

He  received his Ph.D. degree in 2018 in microelectronics at the University of Electronic Science and Technology of China.
His current research interests are low-voltage analog circuits design and low power oversampling ADCs.

Publication

• L. S. Lv, X. Zhou, Z. Qiao, Q. Li. Inverter-based Subthreshold Amplifier Techniques and Their Application in 0.3V Δ?-Modulators [J]. IEEE Journal of Solid-State Circuts(JSSC), 2019.
• L. S. Lv, A. Jain, X. Zhou, J. Beker, Q. Li and M. Ortamnns. A 0.4V Gm-C propotional-integrator-based continous-time ΔΣ modulator with 50kHz BW and 74.4dB SNDR[J]. IEEE Journal of Solid-State Circuts(JSSC), 2019.
• L. S. Lv, Q. Li. 300mV 50kHz 75.9dB SNDR CT ΔΣ Modulator with Inverter-based Feedforward OTAs[C]. In IEEE Int. Symp. Circuits and Systems(ISCAS). Lisbon, 2015,313-316
• L. S. Lv, Q. Li. A low-power CT sigma-delta modulator with 2b/cycle SAR quantizer[C]. In IEEE Int. Midwest Symp Circuits and Systems(MWCAS). Texas, 2014,845-848.

Sheng Chang received the B.S. and M.S. degrees from the University of Electronic Science and Technology of China, Chengdu, China, in 2016 and 2019, respectively.

His research interests include high-speed and high-resolution SAR ADC, digitally-assisted analog circuits design, energy-efficient analog and mixed-signal circuit design.

Publication

S. Chang, X. Zhou, Z. Ding and Q. Li, "A 12-bit 30MS/s SAR ADC with VCO-Based Comparator and Split-and-Recombination Redundancy for Bypass Logic," 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5.

Zhaoming Ding was born in Chongqing, China, in 1989. He received his B.S. degree in Microelectronics from University of Electronic Science and Technology of China, Chengdu, China, in 2012. He received his Ph.D. degree in 2018.

His research interests include analog, mixed-signal circuits, analog-to-digital converters and phase-locked loops.

Publication

• Z. Ding, X. Zhou, Q. Li. A 0.5–1.1V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator[J]. IEEE J. Solid-State Circuits
• Z. Ding, X. Zhou, Q. Li. A 0.5-1.1V 10b adaptive bypassing SAR ADC utilizing oscillation cycle information of VCO-based comparator[C]. in Symp. VLSI Circuits, Hawaii, 2018, 1-2
• Z. Ding, X. Zhou, Q. Li. Delta-measurement low-power SAR ADC architecture with adaptive threshold-first switching[C]. in IEEE Int. Symp. Circuits and Systems (ISCAS), Florence, 2018, 1-4
• Z. Ding, H. Liu, Q. Li. Phase-error cancellation technique for fast-lock phase-locked loop[J]. IET Circuits, Devices & Systems, 2016, 10(5): 417-422
• Z. Ding, H. Liu, Q. Li. A phase error cancellation technique for fast-lock PLL[C]. in IEEE ICSICT, Guilin, 2014, 1-3

Sanfeng Zhang (S’15) received the B.S. degree from School of Microelectronics and Solid-State Electronic, University of Electronic Science and Technology of China, Chengdu, China in 2015 where he is currently pursuing the Ph.D degree in Institute of Integrated Circuits and Systems.

His research interests include analog, mixedsignal circuits in biomedical applications.

Publication

• H. Yao, X. Zhou, S. Zhang, et al, “Fast-settling technique under large electrode offset in integrated biopotential amplifiers”, Biomedical Circuits and Systems Conference. IEEE, 2016:280-283.
• S. Zhang, X. Zhou, et al, "--", 2018 ISSCC Student Research Preview
• S. Zhang, X. Zhou and Q. Li, "A Voltage Swing Robust Pseudo-Resistor Structure for Biomedical Front-end Amplifier," 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Chengdu, 2018, pp. 61-64.

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