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Publications

Journal

  1. Bojun Hu, Sanfeng Zhang, Xiangxin Pan, Xiangyu Zhao, Zhaoming Ding, Xiong Zhou, Shiheng Yang, and Qiang Li, “Sampling and comparator speed-enhancement techniques for near-threshold SAR ADCs,” IEEE Open Journal of Circuits and Systems (OJCAS), accepted.
  2. Sanfeng Zhang, Xiong Zhou, Chen Gao, and Qiang Li, “An AC-coupled instrumentation amplifier achieving 110dB CMRR at 50Hz with chopped pseudoresistors and successive-approximation-based capacitor trimming,” IEEE Journal of Solid-State Circuits (JSSC), vol. 56, no. 1, pp. 277-286, Jan. 2021.
  3. Y. He, X. Yi, Ziji Zhang, B. Ma, and Qiang Li, “A probabilistic prediction based fixed-width Booth multiplier for approximate computing,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCASI), vol. 67, no. 12, pp. 4794-4803, Dec. 2020.
  4. Xiaofei Ma, Yan Lu, Qiang Li, Wing Hung Ki, and Rui P. Martins, “An NMOS digital LDO with NAND-based analog-assisted loop in 28-nm CMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCASI), vol. 67, no. 11, pp. 4041-4052, Nov. 2020.
  5. Zheng Zhu, Xiong Zhou, Yuheng Du, Yao Feng, and Qiang Li, "A 14-bit 4-MS/s VCO-based SAR ADC with deep metastability facilitated mismatch calibration," IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 6, pp. 1565-1576, June 2020.
  6. Xiaofei Ma, Yan Lu, and Qiang Li, "A fully-integrated LDO with 50-mV dropout for power efficiency optimization," IEEE Transactions on Circuits and Systems II: Express Briefs (TCASII), vol. 67, no. 4, pp. 725-729, Apr. 2020.
  7. Xin Si, J.-J. Chen, Y.-N. Tu, W.-H. Huang, J.-H. Wang, Y.-C. Chiu, W.-C. Wei, S.-Y. Wu, X. Sun, R. Liu, S. Yu, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, Qiang Li, and Meng-Fan Chang, “A twin-8T SRAM computation-in-memory unit-macro for multiple-bit CNN based AI edge processors,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 1, pp. 189-202, Jan. 2020.
  8. Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, and Meng-Fan Chang, “A dual-split 6T SRAM-based computing-in-memory unit-macro with fully parallel product-sum operation for binarized DNN edge processor,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCASI), vol. 66, no. 11, pp. 4172-4185, Nov. 2019.
  9. Lishan Lv, Xiong Zhou, Zhiliang Qiao, and Qiang Li, "Inverter-based subthreshold amplifier techniques and their application in 0.3V ΔƩ-modulators," IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 5, pp. 1436-1445, May 2019.
  10. Zhaoming Ding, Xiong Zhou, and Qiang Li, "A 0.5–1.1V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator," IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 4, pp. 968-977, Apr. 2019. (Invited, Special Issue on VLSI Circuits)
  11. Junshi Wang, M. Ebrahimi, Letian Huang, X. Xie, Qiang Li, Guangjun Li, and A. Jantsch, “Efficient design-for-test approach for networks-on-chip,” IEEE Transactions on Computers, vol. 68, no. 2, pp. 198-213, Feb. 2019.
  12. Lishan Lv, Ankesh Jain, Xiong Zhou, Joachim Becker, Qiang Li, and Maurits Ortmanns, "A 0.4V Gm-C proportional-integrator-based continuous-time ΔƩ modulator with 50kHz BW and 74.4dB SNDR," IEEE Journal of Solid-State Circuits (JSSC), vol. 53, no. 11, pp. 3256-3267, Nov. 2018.
  13. Ying Zhao, C. Fang, X. Zhang, X. Xu, T. Gong, Q. Luo, C. Chen, Qi Liu, Hangbing Lv, Qiang Li, Feng Zhang, Ling Li, and Ming Liu, “A compact model for drift and diffusion memristor applied in neuron circuits design,”IEEE Transactions on Electron Devices, vol. 65, no. 10, pp. 4290-4296, Oct. 2018.
  14. C. Chen, M. Xue, Y. Wen, G. Yao, Y. Cui, F. Liao, Z. Yan, L. Huang, S. A. Khan, Min Gao, T. Pan, H. Zhang, W. Jing, D. Guo, Sanfeng Zhang, Hailiang Yao, Xiong Zhou, Qiang Li, Yang Xia, and Yuan Lin, “A Ferroelectric Ceramic/Polymer Composite-Based Capacitive Electrode Array for In Vivo Recordings,” Advanced Healthcare Materials, vol. 6, no. 16, pp. 3667-3677, Aug. 2017.
  15. Chao Liu, Qiang Li, Y. Li, X. Deng, H. Tang, R. Wang, H. Liu, Yongzhong Xiong, "A Ka-band single-chip SiGe BiCMOS phased-array transmit/receive front-end," IEEE Transactions on Microwave Theory and Techniques (TMTT), vol. 64, no. 11, pp. 3667-3677, Nov. 2016.
  16. Zhaoming Ding, Haiqi Liu, and Qiang Li, "Phase-error cancellation technique for fast-lock phase-locked loop," IET Circuits, Devices & Systems, vol. 10, no. 5, pp. 417-422, Sept. 2016.
  17. Junfeng Gao, Guangjun Li, and Qiang Li, "An amplifier-free pipeline-SAR ADC architecture with enhanced speed and energy efficiency," IEEE Transactions on Circuits and Systems −II: Express Briefs (TCASII), vol. 63, no. 4, pp. 341-345, Apr. 2016.
  18. Chao Liu, Qiang Li, Y. Li, X. Li, H. Liu, Yongzhong Xiong, "A fully integrated X-band phased array transceiver in 0.13-µm SiGe BiCMOS technology," IEEE Transactions on Microwave Theory and Techniques (TMTT), vol. 64, no. 2, pp. 575-584, Feb. 2016.
  19. Xiaoyang Wang, Xiong Zhou, and Qiang Li, "A high speed energy-efficient segmented pre-quantize and bypass DAC for SAR ADCs," IEEE Transactions on Circuits and Systems −II: Express Briefs (TCASII), vol. 62, no. 8, pp. 756-760, Aug. 2015.
  20. Chao Liu, Qiang Li, Y. Li, X. Li, H. Liu, and Yongzhong Xiong, “Design of 340 GHz 2× and 4× sub-harmonic mixers using Schottky barrier diodes in silicon-based technology,” Micromachines, vol. 6, no. 5, pp. 592–599, May 2015.
  21. Junfeng Gao, Guangjun Li, and Qiang Li, "A monotonic SAR ADC with system-level error correction," Analog Integrated Circuits and Signal Processing, vol. 84, no. 1, pp. 1-8, May 2015.
  22. Xiaoyang Wang, Hai Huang, and Qiang Li, "Design consideration of ultralow-voltage self-calibrated SAR ADC," IEEE Transactions on Circuits and Systems −II: Express Briefs (TCASII), vol. 62, no. 4, pp. 337-341, Apr. 2015.
  23. Junfeng Gao, Guangjun Li, and Qiang Li, "Central span switching structure for SAR ADC with improved linearity and reduced DAC power," IEICE Electronics Express, vol. 12, no. 5, pp. 1-10, Mar. 2015.
  24. S. Yuan, H. Huang, Q. Liang, and Qiang Li, "Energy efficient comparator for successive approximation register ADCs with application to wireless sensor networks," International Journal of Sensor Networks, vol. 17, no. 2, pp. 122-129, Feb. 2015.
  25. Junfeng Gao, Guangjun Li, and Qiang Li, "High-speed low-power common-mode insensitive dynamic comparator," Electronics Letters, vol. 51, no. 2, pp. 134-136, Jan. 2015.
  26. Shenggang Dong, Xiaoyang Wang, H. Fan, Junfeng Gao, and Qiang Li, "Overview of energy-efficient successive-approximation analog-to-digital converters: state-of-the-art and a design example," Journal of Electronic Science and Technology, vol. 11, no. 4, pp. 372-381, Dec. 2013.
  27. Longfei Wei, Jinyue Ji, Haiqi Liu, Linan Li, and Qiang Li, "Multi-rate SerDes transceiver for IEEE 1394b applications," Journal of Electronic Science and Technology, vol. 10, no. 4, pp. 327-333, Dec. 2012.
  28. Jinyue Ji, Haiqi Liu, and Qiang Li, "A 1-GHz charge pump PLL frequency synthesizer for IEEE 1394b PHY," Journal of Electronic Science and Technology, vol. 10, no. 4, pp. 319-326, Dec. 2012.
  29. Zhiyong Guo, Qiang Li, Haiqi Liu, Bo Yan and Guangjun Li, "An integrated low-voltage ultra-low-power reconfigurable hardware interface in 0.18-µm CMOS," International Journal of Electronics, vol. 98, no. 6, pp. 685-698, June 2011.
  30. Zhiyong Guo, Y. P. Zhang, Bo Yan, Qiang Li, Guangjun Li and H. Rashvand, "Waveform distortion performance evaluation using practical antennas in deterministic multipath impulse radio channels," IET Communications, vol. 5, no. 6, pp. 835-843, Apr. 2011.
  31. Y. P. Zhang, Junjun Wang, Qiang Li, and Xuejun Li, "Antenna-in-package and transmit-receive switch for single-chip radio transceivers of differential architecture," IEEE Transactions on Circuits and Systems −I: Regular Papers (TCASI), vol. 55, no. 11, pp. 3564-3570, Dec. 2008.
  32. Qiang Li, Y. P. Zhang, Kiat-Seng Yeo, and W. M. Lim, "16.6- and 28-GHz fully integrated CMOS RF switches with improved body-floating," IEEE Transactions on Microwave Theory and Techniques (TMTT), vol. 56, no. 2, pp. 339-345, Feb. 2008.
  33. Qiang Li, and Y. P. Zhang, "A 1.5-V 2−9.6-GHz inductorless low-noise amplifier in 0.13-μm CMOS," IEEE Transactions on Microwave Theory and Techniques (TMTT), vol. 55, no. 10, pp. 2015-2023, Oct. 2007. (No. 1 of the top 10 papers accessed in MTT, October 2007.)
  34. Y. P. Zhang, and Qiang Li, "Performance of UWB impulse radio with planar monopoles over on-human-body propagation channel for wireless body area networks," IEEE Transactions on Antennas and Propagation (TAP), vol. 55, no. 10, pp. 2907-2914, Oct. 2007.
  35. Qiang Li, and Y. P. Zhang, "CMOS T/R switch design: towards ultra-wideband and higher frequency," IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 3, pp. 563-570, Mar. 2007. (No. 36 of the top 100 documents accessed in IEEEXplore, March 2007.)
  36. Qiang Li, and Y. P. Zhang, "Alternative approach to low-noise amplifier design for ultra-wideband applications," International Journal of RF and Microwave Computer-Aided Engineering, vol. 17, no. 2, pp. 153-159, Mar. 2007.
  37. Y. P. Zhang, Qiang Li, Wei Fan, Chewhoe Ang, and He Li, "A differential CMOS T/R switch for multistandard applications," IEEE Transactions on Circuits and Systems −II: Express Briefs (TCASII), vol. 53, no. 8, pp. 782-786, Aug. 2006.

Conference

  1. Ruiqi Guo, Zhiheng Yue, Xin Si, T. Hu, H. Li, L. Tang, Y. Wang, L. Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, and Shouyi Yin, “A 5.99-to-691.1 TOPS/W tensor-train in-memory-computing processor using bit-level-sparsity-based optimization and variable-precision quantization,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United States, Feb. 13-22, 2021.
  2. Sanfeng Zhang, Chen Gao, Xiong Zhou, and Qiang Li, “A 130dB-CMRR instrumentation amplifier with common-mode replication,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United States, Feb. 16-20, 2020.
  3. Pengfei Zhai, Xiong Zhou, Yan Cai, Zheng Zhu, Fan Zhang, and Qiang Li, “A scalable 20GHz on-die power supply noise analyzer with compressed sensing,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United States, Feb. 16-20, 2020.
  4. Xin Si, Y.-N. Tu, W.-H. Huang, J.-W. Su, P.-J. Lu, J.-H. Wang, T.-W. Liu, S.-Y. Wu, R. Liu, Y.-C. Chou, Z. Zhang, S.-H. Sie, W.-C. Wei, Y.-C. Lo, T.-H. Wen, T.-H. Hsu, Y.-K. Chen, W. Shih, C.-C. Lo, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, N.-C. Lien, W.-C. Shih, Y. He, Qiang Li, and Meng-Fan Chang, “A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United States, Feb. 16-20, 2020.
  5. Ying Zhao, Ling Li, Y. Peng, Q. Li, G. Yang, X. Chuai, Qiang Li, G. Han, and Ming Liu, "Surface potential-based compact model for negative capacitance FETs compatible for logic circuit: with time dependence and multidomain interaction," IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, United States, Dec. 7-11, 2019.
  6. Pengfei Zhai, Xiong Zhou, Yan Cai, Zheng Zhu, Fan Zhang, Z. Lin, and Qiang Li, "A multi-slice VCO-based quantizer for on-chip power supply noise analysis achieving 0.11 (mV)2/sqrt(MHz) noise floor," IEEE Asian Solid-State Circuits Conference (A-SSCC), Macau, Nov. 4-7, 2019.
  7. Xin Si, J.-J. Chen, Y.-N. Tu, W.-H. Huang, J.-H. Wang, W.-C. Wei, S.-Y. Wu, X. Sun, R. Liu, S. Yu, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, Qiang Li, and Meng-Fan Chang, “A twin-8T SRAM computation-in-memory macro for multiple-bit CNN based machine learning,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United States, Feb. 17-21, 2019.
  8. Haiwen Chen, Xiong Zhou, Qiang Yu, Fan Zhang, and Qiang Li, "A >3GHz ERBW 1.1-GS/s 8-bit two-step SAR ADC with recursive-weight DAC," Symposium on VLSI Circuits, Honolulu, HI, United States, June 18-22, 2018.
  9. Zhaoming Ding, Xiong Zhou, and Qiang Li, "A 0.5-1.1V 10b adaptive bypassing SAR ADC utilizing oscillation cycle information of VCO-based comparator," Symposium on VLSI Circuits, Honolulu, HI, United States, June 18-22, 2018. (Invited for JSSC Special Issue on VLSI Circuits)
  10. Zhaoming Ding, X. Zhou, and Qiang Li, “Delta-measurement low-power SAR ADC architecture with adaptive threshold-first switching,” IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 27-30, 2018.
  11. Xiaofei Ma, Yan Lu, Rui P. Martins, and Qiang Li, “A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United States, Feb. 11-15, 2018.
  12. W.-S. Khwa, J.-J. Chen, J.-F. Li, Xin Si, E.-Y. Yang, X. Sun, R. Liu, P.-Y. Chen, Qiang Li, S. Yu, and Meng-Fan Chang, “A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United States, Feb. 11-15, 2018.
  13. Sanfeng Zhang, Xiong Zhou, Chen Gao, Xu Cheng, Xiaoyang Zeng, and Qiang Li, "-," International Solid-State Circuits Conference (ISSCC): Student Research Preview, San Francisco, CA, United States, Feb. 11-15, 2018.
  14. Hailiang Yao, Xiong Zhou, Sanfeng Zhang, and Qiang Li, "Fast-settling technique under large electrode offset in integrated biopotential amplifiers," IEEE Biomedical Circuits and Systems Conference (BioCAS), Shanghai, China, Oct 17-19, 2016.
  15. Xiong Zhou, Qiang Li, S. Kilsgaard, F. Moradi, S. Kappel, and P. Kidmose, "A wearable ear-EEG recording system based on dry-contact active electrodes," Symposium on VLSI Circuits, Honolulu, HI, United States, June 13-17, 2016, pp. 260-261.
  16. Lishan Lv, Xiong Zhou, and Qiang Li, "A 0.3-V 70.8-dB DR low-power continuous-time ΔƩ modulator," International Solid-State Circuits Conference (ISSCC): Student Research Preview, San Francisco, CA, United States, Jan. 31-Feb. 4, 2016.
  17. Chao Liu, Qiang Li, Y. Li, X. Li, H. Liu, and Yong-Zhong Xiong, "An 890mW stacked power amplifier using SiGe HBTs for X-band multifunctional chips," 41st European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, Sept. 14-18, 2015.
  18. Xiong Zhou, Zhiliang Qiao, Lishan Lv, and Qiang Li, “Subthreshold OTA and its applications to ultra-low voltage ADCs”, 11th IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Singapore, June 1-4, 2015. (Invited)
  19. Lishan Lv, and Qiang Li, "300mV 50kHz 75.9dB SNDR CT ΔƩ modulator with inverter-based feedforward OTAs," IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 24-27, 2015.
  20. Y. He, Z. Zhang, B. Ma, J. Li, S. Zhen, P. Luo, and Qiang Li, "A fast and energy efficient binary-to-pseudo CSD converter," IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 24-27, 2015.
  21. Kun Ao, Y. He, L. Li, Yong Wang, and Qiang Li, "A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy," 14th International Symposium on Integrated Circuits (ISIC), Singapore, Dec. 10-12, 2014.
  22. Zhiliang Qiao, Xiong Zhou, and Qiang Li, "A 250mV 77dB DR 10kHz BW SC ΔΣ modulator exploiting subthreshold OTAs," 40th European Solid-State Circuits Conference (ESSCIRC), Venice, Italy, Sept. 22-26, 2014.
  23. Lishan Lv, and Qiang Li, " A low-power CT sigma-delta modulator with a 2b/cycle SAR quantizer," IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), College Station, TX, United States, Aug. 3-6, 2014.
  24. Xiaoyang Wang, Xiong Zhou, and Qiang Li, "A 10-bit 150MS/s SAR ADC with parallel segmented DAC in 65nm CMOS," IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, June 1-5, 2014.
  25. Junfeng Gao, Bo Chen, Guangjun Li, and Qiang Li, "A 13-bit 200MS/s pipeline ADC in 0.13µm CMOS," IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, United States, Aug. 4-7, 2013.
  26. Jingjing Tian, Guangjun Li, and Qiang Li, "Hardware-efficient parallel structures for linear-phase FIR digital filter," IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, United States, Aug. 4-7, 2013.
  27. Hai Huang, Xiaoyang Wang, and Qiang Li, "Design consideration of ultra-low voltage self-calibrated SAR ADC," 10th International Conference on Sampling Theory and Applications (SampTA), Bremen, Germany, July 1-5, 2013. (Invited)
  28. Hai Huang, Kun Ao, and Qiang Li, "A 0.5V rate-resolution scalable SAR ADC with 63.7dB SFDR," IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, May 19-23, 2013.
  29. Longfei Wei, Jinyue Ji, Haiqi Liu, and Qiang Li, "A multi-rate SerDes transceiver for IEEE 1394b applications," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Kaohsiung, Taiwan, Dec. 2-5, 2012.
  30. Chuanping Yan, Guangjun Li, and Qiang Li, "A fast correlation based background digital calibration for pipelined ADCs," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Kaohsiung, Taiwan, Dec. 2-5, 2012.
  31. Xiong Zhou, and Qiang Li, "A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS," IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, United States, Sept. 9-12, 2012.
  32. Shan Qing, Guangjun Li, and Qiang Li, "A fast-convergence and robust digital calibration algorithm for a 14-bit 200-MS/s hybrid pipelined-SAR ADC," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, United States, Aug. 5-8, 2012.
  33. Xiong Zhou, and Qiang Li, "A 160mV 900nW 8b 55kS/s SAR ADC," International Solid-State Circuits Conference (ISSCC): Student Research Preview, San Francisco, CA, United States, Feb. 19-23, 2012.
  34. Jianjun Fan, Qiang Li, and Guangjun Li, "Blind adaptive calibration of timing error for two-channel time-interleaved ADCs," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seattle, United States, Aug. 1-4, 2010.
  35. Qiang Li, and Y. P. Zhang, "Waveform distortion and performance of impulse radio with realistic antennas in deterministic multipath channels," 67th IEEE Vehicular Technology Conference: VTC2008-Spring, Singapore, May 11-14, 2008.
  36. Qiang Li, Roy Tan, and Rajinder Singh, "A 1-V 36-µW low-noise adaptive interface IC for portable biomedical applications," 33rd European Solid-State Circuits Conference (ESSCIRC), Munich, Germany, Sept. 11-13, 2007, pp. 288-291.
  37. Qiang Li, Y. P. Zhang, and J. S. Chang, "An inductorless low-noise amplifier with noise cancellation for UWB receiver front-end," 2nd IEEE Asian Solid-State Circuits Conference (ASSCC), Hangzhou, China, Nov. 13-15, 2006, pp. 267-270.
  38. Qiang Li, and Y. P. Zhang, "Gain-flatness considerations on the ultra-wideband low-noise amplifier design," 17th IEEE Asia Pacific Microwave Conference (APMC), Suzhou, China, Dec. 4-7, 2005, pp. 2588-2591.
  39. Qiang Li, and Y. P. Zhang, "Implementation oriented analysis of ultra-wideband front-end," 10th International Symposium on Integrated Circuits, Devices and Systems (ISIC), Singapore, Sept. 8-10, 2004.

Patent

  1. "An Active Electrode Having a Closed-Loop Unit-Gain Amplifier with Chopper Modulation," US 2017/0281037, WO/2016/096030, filed Dec. 19, 2014.
  2. "Triple Well Transmit-Receive Switch Transistor," US 8,288,829, WO/2008/036047, 2012/10/16.
  3. "Low-Noise Amplifier Circuit with Noise Cancellation and Increased Gain," US 7,843,270, WO/2008/041948, 2010/10/30.